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Arm CoreLink GIC-600 Generic Interrupt Controller Technical Reference Manual : Interchip signals

Interchip signals

The following table shows the GIC-600 interchip signals.

Table A-9 Interchip signals

Signal name Forward or reverse Source or destination Description
icdrtready Reverse Remote chip → Distributor AXI4-Stream compliant bus for communication between the Distributor and a remote chip. It is fully credited and must never backpressure. It can be sent over any free-flowing interconnect.
icdrtvalid Forward Distributor → Remote chip
icdrtdata[63:0] Forward
icdrtlast Forward
icdrtwakeup Forward Registered wake signal to indicate that a message is arriving or is about to arrive on the icdr bus. Signals icdrtvalid and icdrtready control data transfer.
icdrtdest[variable:0]a Forward

Specifies the destination remote chip.

This signal is only present on the Distributor.

See AXI4-Stream interfaces in Functional integration guidelines of the Arm®CoreLink™ GIC‑600 Generic Interrupt Controller Configuration and Integration Manual for more information.

icdrtkeep Forward

Indicates the data bytes that must be transferred.

This signal is only present on the Distributor.

icrdtready Reverse AXI4-Stream compliant bus for communication between the remote chip and the Distributor. It is fully credited and can be sent over any free-flowing interconnect.
icrdtvalid Forward Remote chip → Distributor
icrdtdata[63:0] Forward
icrdtlast Forward
icrdtwakeup Forward Registered wake signal to indicate that a message is arriving or is about to arrive on the icrd bus. Signals icrdtvalid and icrdtready control data transfer.
a The variable is configuration-dependent.
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