Distributor ACE-Lite master interface
The GICD uses the AMBA® AXI4 ACE-Lite master interface to access LPI Property and Pending tables. If LPIs are not supported, then this interface is not present.
The interface can be configured to be 64-bit, 128-bit, or 256-bit wide.
The following table shows the issuing capabilities of the Distributor ACE-Lite master interface.
Table 2-4 Distributor ACE-Lite master interface issuing capabilities
|256-bit aligned read and writes to any Pending table||3||3||3|
|8-bit read and writes to any Pending table||1||1||1|
|256-bit aligned reads to the Property table||1||0||1|
|8-bit reads to the Property table||4||0||4|
Each transaction uses a unique transaction ID, and properties come from either the GICR_PROPBASER or GICR_PENDBASER registers according to the destination. There is one copy of the attribute fields for all GICR_PROPBASER registers and another for all GICR_PENDBASER registers, so software must program these registers to a consistent value in all Redistributors.
The ACE-Lite master port cannot issue barriers or Cache Maintenance Operations (CMOs). However, it can issue shareable, ReadOnce and WriteUnique, transactions if programmed to do so.
See Memory access and attributes for more information.
The a<x>user_m signal outputs the GICR_TYPER.ProcessorNumber of the core that is associated with each transaction, but it can be ignored and it is not necessary to route it anywhere else.