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ITS ACE-Lite slave interface

The ITS AMBA® AXI4 ACE-Lite slave interface has a configurable width of 64 bits, 128 bits, or 256 bits. The slave, master, and address data widths must match.

The ITS ACE-Lite slave port contains only the GITS_TRANSLATER register. See the Arm® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 for more information.

If the bypass switch configuration option is selected, the port accepts all ACE-Lite traffic, and filters accesses to the ITS based on an address match set by the ITS base address tie-off target_address[<n>ADDR_WIDTH-17:0]. Without the bypass switch, the upper bits of the address, 16 and above, are ignored, and the system address decoders must ensure that only relevant ITS writes arrive at the ITS.

The ACE-Lite slave interface ignores all a<x>snoop, a<x>cache, a<x>domain, and a<x>prot information other than to filter CMOs and Barriers to ensure that it replies in a protocol-compliant manner.

To generate an LPI, the ITS requires the DeviceID of the issuing master. For PCIe, the DeviceID is derived from the RequestorID.

The GIC-600 supports two different methods for deriving the DeviceID:

  • When using the MSI-64 config parameter, the write to GITS_TRANSLATER is converted to 64-bit accesses at an unmapped system address and the DeviceID is transferred in the upper 32 bits of the access. In this case, only burst length 1, 64-bit ACE-Lite writes are accepted.
  • When not using MSI-64, the DeviceID is transported on the AWUSER bus with the address (AW) phase of the register access. In this case, burst length 1, 32-bit or 16-bit writes are accepted.

The DeviceID must be transferred using a method that cannot be spoofed by malicious software.


These two modes cannot be mixed on a single ITS.

If the bypass switch is configured, it includes a transaction tracker that ensures PCIe ordering requirements are met. There are two options that are based on the full_bypass_tracker tag:

0 = A simple scheme is used, which ensures that all previous transactions sent downstream have completed before forwarding an MSI to the ITS, and conversely, that the ITS has accepted all MSIs before continuing to send traffic downstream.

1 = A more complex scheme, which allows continuous downstream traffic including interleaved MSIs, unless the buffer slots become full. There are two buffers, bypass_max_outstanding, which specifies the number of concurrent downstream transactions allowed and bypass_interrupt_count, which specifies the number of concurrent MSIs that can be waiting for their prerequisite transactions to complete.


The ITS slave port contains only write-only registers, therefore the read channel always uses the simple transaction tracker.

If the bypass switch is configured, the slave and master ports must both have the same data width and the same address width.

If the Distributor and ITS both share the ACE-Lite slave port, the port properties match those of the Distributor ACE-Lite slave port, which are described in Distributor ACE-Lite slave interface.

The following table shows the acceptance capabilities of the ITS ACE-Lite slave interface.

Table 2-10 ITS ACE-Lite slave interface acceptance capabilities

Attribute With bypass switch Without bypass switch
Combined acceptance capability Read acceptance capability + Write acceptance capability 3
Read acceptance capability 128 1
Read data reorder depth 128 1
Write acceptance capability 128 or bypass_max_outstanding 2

The ITS ACE-Lite slave interface has an associated awakeup signal. To ensure that incoming traffic wakes the ITS correctly when it is clock gated hierarchically through the Q-Channel, awakeup must be driven from a registered version of awvalid and arvalid. To prevent spurious wake events, ensure that the awakeup signal is registered cleanly.

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