Implementation-defined features reference
The GIC-600 implements features that are defined in the GICv3 Architecture. Many of these features also have options in the GICv3 Architecture, which determine behavior that is specific to the GIC-600. These features and options are configurable at build time.
The following table summarizes features in the Arm® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 that are used by the GIC-600, and which have options that are implementation-defined. The table also gives references to sections within this manual that provide information about implementation-defined behavior that is specific to the GIC-600.
Table B-1 Declared implementation-defined features
|GICv3 Architecture feature||Architectural specification reference||Description|
|1 of N model||Introduction||Models for handling interrupts||See 1 of N SPI interrupt selection.|
|Direct LPI support||GIC partitioning||The GIC logical components||Direct LPI support is by configuration if there are no ITS blocks in the system.|
|ITS to Redistributor communications||
Locality-specific peripheral interrupts and the ITS
|This is done over a fully credited AXI4-Stream.|
|INTIDs||Distribution and routing of interrupts||INTIDs||16-bit width when supporting LPIs, otherwise the width is set to support the number of SPIs and SGIs.|
|All error cases||-||Pseudocode throughout the document||All errors are reported through error records, see Reliability, Accessibility, and Serviceability.|
|Message-based SPIs||Physical interrupt handling and prioritization||Shared peripheral interrupts||Pending bits for level sensitive SPIs that are set by writes to GICD_SETSPI_* or GICA_SETSPI_* are not affected by writes to GICD_ICPENDRn. Writes to GICD_CLRSPI_* or GICA_CLRSPI_* have no effect on pending bits set by GICD_ISPENDRn.|
|Interrupt grouping||Physical interrupt handling and prioritization||Interrupt grouping||All implemented SPIs, SGIs, and PPIs have programmable groups.|
|Interrupt enables||Physical interrupt handling and prioritization||Enabling individual interrupts||All SGIs have a programmable enable.|
|Interrupt prioritization||Physical interrupt handling and prioritization||Interaction of group and individual interrupt enables||Interrupts that are disabled through the GICC_CTLR register or the ICC_CTLR_* registers are not considered in the selection of the highest pending interrupt and do not block fully enabled interrupts of a lower priority.|
|Interrupt prioritization||GIC-600 supports 32 priority levels, 16 for LPIs that are always Non-secure.|
|Effects of disabling interrupts||Physical interrupt handling and prioritization||Effect of disabling interrupts||Interrupts are set pending irrespective of the GICD_CTLR.EnableGrp* settings.|
|Changing priority||Physical interrupt handling and prioritization||
Changing the priority of enabled PPIs, SGIs, and SPIs.
|Reprogramming a IPRIORITYRn register does not change the priority of an active interrupt but causes a pending and not active interrupt to be recalled from the CPU interface so that the new value can be applied.|
|Direct LPI registers||Locality-specific peripheral interrupts and the ITS||LPIs||The GICR_SETLPIR, GICR_CLRLPIR, GICR_INVLPIR, GICR_INVALLR, and GICR_SYNCR are supported in configurations that support LPIs but have no ITS anywhere in the system. If there is an ITS, these registers, and their locations, are RAZ/WI.|
|LPI caching||Locality-specific peripheral interrupts and the ITS||LPIs||See LPI caching and Interrupt translation service (ITS).|
|LPI configuration tables||Locality-specific peripheral interrupts and the ITS||LPI configuration tables||
The GIC-600 has one GICR_PROPBASER register for all cores on a chip and therefore points at a single table. Each chip in a multichip configuration can point to a copy of the table in local memory. See CommonLPIAff in Table 4-23 GICR_TYPER bit assignments for more information.
When interrupts are sent between chips, they keep the properties associated with them until the next invalidate. All property fetches are always from the offset specified in the GICR_PROPBASER of the issuing chip.
|LPI Pending tables||Locality-specific peripheral interrupts and the ITS||LPI Pending tables||Refer to the GICv3 Architecture description.|