A Private Peripheral Interrupt identifies an interrupt source, such as a timer, that is private to the core, and which is independent of the same source for another core. PPIs are typically used for peripherals that are tightly coupled to a particular core.
Interrupts that are connected to the PPI inputs associated with one core, are only sent to that core. Each core processes a PPI independently of other cores. The settings of a PPI are also independent for each core.
A PPI is unique to one core. However, the PPIs to other cores can have the same INTID. Up to 16 PPIs can be recorded for each target core, where each PPI has a different INTID in the range ID16-ID31.
PPI signals are active-LOW level-sensitive by default. However, you can set a PPI signal to be either level-sensitive or edge-triggered using GICR_ICFGR1, see the Arm® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0.
The GIC-600 provides an option, through parameters, to include one or both a synchronizer and inverter on each PPI interrupt wire. See Redistributor PPI signals for more information.
For information about the purpose of each PPI used by the processor core in your system, refer to the processor Technical Reference Manual.