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A Shared Peripheral Interrupt is generated by a peripheral that is accessible across the whole system, such as a USB receiver, and which can be routed to several cores. SPIs are typically used for peripherals that are not tightly coupled to a specific core.

You can program each SPI to target either a particular core or any core. Activating a SPI on one core activates the SPI for all cores. That is, the GIC-600 allows at most one core to activate a SPI. The settings for each SPI are also shared between all cores.

SPIs are generated either by wire inputs or by writes to the ACE-Lite slave programming interface. The GIC-600 can support up to 960 SPIs corresponding to the external spi signal on the SPI Collator. The number of SPIs available depends on the implemented configuration. The permitted values are ID32-ID960, in steps of 32. The first SPI has an ID number of 32.

You can configure whether each SPI is triggered on a rising edge or is active-HIGH level-sensitive. The GIC-600 provides an option, through a parameter, to include one or both a synchronizer and inverter on each SPI interrupt wire.

The GIC-600 uses the SPI Collator to convert wire-based interrupts into messages to reduce system wiring, and to allow more aggressive clock gating of the GIC to reduce power consumption. See SPI Collator for more information.

SPIs are programmed through the GICD register address space, which is spread coherently across all configured chips to provide a single view to the Operating System (OS).

You can add a pending state to a valid SPI using GICD_SETSPI_NSR or GICD_SETSPI_SR, see the Arm® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0.

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