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Connecting the chips

To connect the chips in a multichip configuration requires you to follow a procedure.

The procedure for connecting the chips in a multichip configuration is as follows:


  1. Ensure that the values of the chip_id tie-off input signals to all chips are correct.
  2. Ensure that all Group enables in the GICD_CTLR register are disabled and GICD_CTLR.RWP == 0.
  3. Designate a chip, chip x, to own the Routing table.


    You can designate a different chip later if required.
  4. In a single register write, program GICD_CHIPRx with:
    1. GICD_CHIPRx.ADDR so that each chip can forward messages to chip x.


      This value is driven by the AXI4-Stream input interface icdrtdest signal. Depending on how cross-chip messages are routed, this value can be the chip_id, or a more complex identifier.
    2. GICD_CHIPRx.SPI_BLOCK_MIN and GICD_CHIPRx.SPI_BLOCKS to appropriate values for the SPIs that chip x owns.
      Example: If the range of interrupt ids for chip x is ID96-ID159:
      • Set SPI_BLOCK_MIN = (96 - 32) / 32 = 2.
      • Set SPI_BLOCKS = (159 - 96 + 1) / 32 = 2.
    3. GICD_CHIPRx.SocketState = 1.
  5. To check that the writes are successful, read GICD_CHIPRx.


    The writes might fail due to security settings, an overlapping or non-existent SPI, or if another update is still in progress. If the accesses fail, then GICD_CHIPRx.SocketState == 0, indicating that the chip is offline.
  6. To check that the actions of this sequence have executed correctly, read the following register fields and ensure that their values are as follows:
    1. GICD_CHIPSR.RTS == 2 (Consistent).
    2. GICD_DCHIPR.rt_owner == chip x.
    3. GICD_DCHIPR.PUP == 0.
    Results: Chip x is now in the consistent state and ready to accept connections to other chips in the system configuration.
Connecting additional chips:
  1. Set the relevant address and SPI ownership information of the next chip you want to connect to, chip y, by writing to GICD_CHIPRy.


    You can do this through any chip that is already connected, or more efficiently by writing to the chip that owns the Routing table, chip_id == rt_owner.
  2. Poll GICD_DCHIPR until bit PUP == 0, indicating that the connection is complete.
  3. To check that the write to GICD_CHIPRy is accepted, read GICD_CHIPRy.
    For each chip connection, repeat steps 7 through 9.


    • You must consider that data read from GICD_CHIPRn is valid only when GICD_DCHIPR.PUP == 0, otherwise the data might be updating.
    • If you are connecting a new chip, the accesses must be done through a chip that is in the Consistent state and not by writing to the new chip directly.
    • If you access GICD_CHIPSR while a chip is being connected, it shows RTS == Updating, register GICD_DCHIPR bit PUP is set, indicating that the Routing table is updating, so the values cannot be trusted.
    • Adding or removing a chip when GICD_CTLR group enables are set is unpredictable. To check that group enables are off, software must poll GICD_CTLR.RWP.
    • If you are connecting together multiple different instances of the GIC-600, the settings for the following parameters must match in all chips:
      • All affinity widths (max_affinity_width*).
      • Number of SPI blocks supported (spi_blocks).
      • LPI support type (lpi_support).
      • Disable Security settings (ds_value).
      • Total number of chips supported (chip_count).
      • Chip address width (chip_addr_width).
      • Chip affinity select level (chip_affinity_select_level).
      • Maximum number of cores on any single chip (max_pe_on_chip).
    • If any chip in the system has an ITS block, parameter its_type_support = full, then direct injection LPI registers are not supported.

    See the Arm®CoreLink™ GIC‑600 Generic Interrupt Controller Configuration and Integration Manual for information on configuration parameters and their options.

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