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Isolating a chip from the system

You can isolate a chip from the system.

To isolate a chip from the system, use the following procedure:

  1. Ensure that all cores on the chip are asleep by setting GICR_WAKER.ProcessorSleep.
  2. Ensure all ITS blocks on the chip are disabled and the buses are quiesced by using the qreqn_its<n> Q-Channel interfaces.
  3. Ensure that LPIs from other chips are not routed to this chip.
  4. Attempt to enter the CONFIG state (pstate = 0x9).

    If the GIC is idle and all credits are returned, it accepts the request to go into CONFIG state, otherwise it denies the request and remains in RUN state.


    All SPIs must return to their own chip before a request is accepted. This means that SPIs that are enabled and pending, but targeting a core on a remote chip where the relevant CPU group is disabled, prevent transition into the CONFIG state.

    When in the CONFIG state, any cross-chip messages that change the internal state are held in the cross-chip interface, and all messages assert pactive. If pactive asserts while attempting to enter a lower power state, you must return to RUN (pstate == 0x0).

  5. When in CONFIG state, any required state can be saved.


    Writing GICD_CHIPR or GICD_DCHIPR for any purpose other than to restore saved values after a hardware reset is unpredictable.
  6. Power down the Redistributors using the GICR_PWRR registers.
  7. If required, flush the LPI cache using GICR_WAKER.Sleep.

    Arm recommends that if wake-on-interrupt is required, LPIs from other chips do not target this chip while the chip is being powered down (step 3), and must be routed back while the chip is in the OFF state.

    LPIs that arrive after sleep is set in the CONFIG state are dropped.

  8. Attempt to enter the OFF state.


    If pactive is raised, return to the CONFIG state.
  9. Use the Q-Channel to put the GIC into a safe mode to reset.


    If the SPI_Collator is in a different domain to the Distributor and only one of the domains is being reset, then the Power Q-Channel must have also accepted before the reset can occur. This might require masking interrupts outside of the GIC to ensure that all interrupt lines have reached their idle state.

    Power up is the reverse of the powerdown sequence. However, you must ensure that the Routing table is restored before other registers, else the behavior is unpredictable. Restoring values to the Routing table that are not exactly the same as those read out before a reset, can cause unpredictable behavior.


    Accesses to GICD_CTLR continue to be broadcast to the isolated chip, which requests wakeup.
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