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Chip Status Register, GICD_CHIPSR

This register allows Secure software to access the status of the chip in a multichip configuration. A single copy of this register exists on each chip in a multichip configuration.

The GICD_CHIPSR characteristics are:

Usage constraintsOnly accessible by Secure accesses.
ConfigurationsAvailable in all multichip configurations.
AttributesSee Distributor registers (GICD/GICDA) summary.

The following figure shows the bit assignments.

Figure 4-6 GICD_CHIPSR bit assignments

The following table shows the bit assignments.

Table 4-9 GICD_CHIPSR bit assignments

Bits Name Function
[31:6] -


[5:4] RTS

Route Table Status:

0b00 = Disconnected.

0b01 = Updating.

0b10 = Consistent.

0b11 = Reserved.

RAZ/WI = single chip configuration.

[3] - Reserved, SBZ.
[2] GTO

Gating Transaction Ongoing:

0 = No accesses.

1 = Accesses ongoing.

This bit is RO.

[1] GTS

Gating Status:

0 = Not gated.

1 = Gated.

This bit is RO.

[0] GTR

Gating Request:

0 = Do not gate.

1 = Request to gate.

This bit is RO.

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