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Distributor Control Register, GICD_CTLR

This register enables interrupts and affinity routing.

The GICD_CTLR characteristics are:

Usage constraintsThe EnableGrp* bits and the RWP bit must be 0 before the DS bit can be updated. A write that sets the DS bit must also set the EnableGrp* bits to 0.
ConfigurationsAvailable in all GIC-600 configurations.
AttributesSee Distributor registers (GICD/GICDA) summary.

The following figure shows the bit assignments.

Figure 4-1 GICD_CTLR bit assignments


The following table shows the bit assignments.

Table 4-3 GICD_CTLR bit assignments

Bits Name Function
[31] RWP

Register Write Pending.

1 = Register write in progress.

Resets to 0. This bit is read only.

[30:8] - Reserved.
[7] E1NWF

Enable 1 of N Wakeup Functionalitya.

Resets to 0.

[6] DS

Disable Securitya.

Resets to ds_value == 1.

[5] ARE_NS

Affinity Routing Enable, Non-secure statea.

Resets to 1.

[4] ARE_S

Affinity Routing Enable, Secure statea.

Resets to 1.

[3] - Reserved.
[2] EnableGrp1S

Enable Secure Group 1 interruptsa.

Resets to 0.

[1] EnableGrp1NS

Enable Non-secure Group 1 interruptsa.

Resets to 0.

[0] EnableGrp0

Enable Group 0 interruptsa.

Resets to 0.

Note

For information about the different Security states for this register, see Field descriptions, GICD_CTLR, Distributor Control Register, in the Arm® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0.
a See the Arm® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0
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