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Interrupt Controller Type Register, GICD_TYPER

This register returns information about the configuration of the GIC-600. You can use this register to determine the number of Security states, the number of INTIDs, and the number of processor cores that the GIC supports.

The GICD_TYPER characteristics are:

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all GIC-600 configurations.
AttributesSee Distributor registers (GICD/GICDA) summary.

The following figure shows the bit assignments.

Figure 4-2 GICD_TYPER bit assignments

The following table shows the bit assignments.

Table 4-4 GICD_TYPER bit assignments

Bits Name Function
[31:26] - Reserved, returns 0b000000.
[25] No1N

1 of N SPI:

0 = The GIC-600 supports 1 of N SPI interrupts.

[24] A3V

Affinity level 3 values.

Depending on the configuration, returns either:

0 = The GIC-600 Distributor only supports zero values of Affinity level 3.

1 = The GIC-600 Distributor supports nonzero values of Affinity level 3.

[23:19] IDbits

Interrupt identifier bits:

0b01111 = The GIC-600 supports 16 interrupt identifier bits.

[18] DVIS

Direct Virtual LPI injection support:

0 = The GIC-600 does not support Direct Virtual LPI injection.

See the Arm® GICv3 and GICv4 Software Overview.

[17] LPIS

Indicates whether the implementation supports LPIs.

Depending on the configuration, returns either:

0 = LPIs are not supported.

1 = LPIs are supported.

[16] MBIS

Message-based interrupt support:

1 = The GIC-600 supports message-based interrupts.

[15:11] - Reserved, returns 0b00000.
[10] SecurityExtn

Security state support.

Depending on the configuration, returns either:

0 = The GIC-600 supports only a single Security state.

1 = The GIC-600 supports two Security states.

When GICD_CTLR.DS == 1, this field is RAZ.

[9:8] - Reserved, returns 0b00.
[7:5] - Reserved, returns 0b000.
[4:0] ITLineNumber

Number of SPIs divided by 32.

Returns the number of SPIs divided by 32. The permitted values for this field are 0-30 (992 SPIs maximum).

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