You copied the Doc URL to your clipboard.

Interrupt Error Registers, GICD_IERRRn

These registers indicate the error status of a SPI. Each register monitors 32 SPIs and the GIC-600 has 30 registers, GICD_IERRR1-GICD_IERRR30.

The GICD_IERRRn characteristics are:

Usage constraintsThe Distributor provides up to 30 registers to support 960 SPIs. If you configure the GIC-600 to use fewer than 960 SPIs, it reduces the number of registers accordingly. For locations where interrupts are not implemented, the register is RAZ/WI.
ConfigurationsAvailable in all GIC-600 configurations.
AttributesSee Distributor registers (GICD/GICDA) summary.

The following figure shows the bit assignments.

Figure 4-10 GICD_IERRRn bit assignments


The following table shows the bit assignments.

Table 4-13 GICD_IERRRn bit assignments

Bits Name Function
[31:0] Status

Indicates whether a SPI is in an error state:

0 = If read, the SPI is not in an error state and programming is valid. Write has no effect.

1 = If read, the SPI is in an error state and programming is not valid. Write clears the error.

Note

The SPI that a bit refers to depends on its bit position and the base address offset of the GICD_IERRRn.
Was this page helpful? Yes No