Counter Enable Clear Register 0, GICP_CNTENCLR0
This register contains the disables for each event counter. The GIC-600 supports five event counters.
The GICP_CNTENCLR0 characteristics are:
|Usage constraints||There are no usage constraints.|
|Configurations||Available in all GIC-600 configurations.|
|Attributes||See GICP register summary.|
The following figure shows the bit assignments.
Figure 4-48 GICP_CNTENCLR0 bit assignments
The following table shows the bit assignments.
Table 4-64 GICP_CNTENCLR0 bit assignments
Counter disable. The CNTEN[n] bit is the disable for counter n. This field resets to an unknown value.
Writing 1 to a bit location clears the enable for the associated counter.
Writing 0 to a bit location has no effect. To enable a counter, use the GICP_CNTENSET0 register.
Reads return the state of the counter enables.
Counter n is disabled when CNTEN[n] == 0 or GICP_CR.E == 1.