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Counter Enable Set Register, GICP_CNTENSET0

These registers contain the enables for each event counter. The GIC-600 supports five event counters.

The GICP_CNTENSET0 characteristics are:

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all GIC-600 configurations.
AttributesSee GICP register summary.

The following figure shows the bit assignments.

Figure 4-47 GICP_CNTENSET0 bit assignments

The following table shows the bit assignments.

Table 4-63 GICP_CNTENSET0 bit assignments

Bits Name Function
[31:5] - Reserved, RAZ
[4:0] CNTEN

Counter enable.

The CNTEN[n] bit is the enable for counter n. This field resets to an unknown value.

Writing 1 to a bit location sets the enable for the associated counter.

Writing 0 to a bit location has no effect. To disable a counter, use the GICP_CNTENCLR0 register.

Reads return the state of the counter enables.

Counter n is enabled when CNTEN[n] == 1 and GICP_CR.E == 1.

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