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Interrupt Configuration Register, GICP_IRQCR

This register controls the counter interrupts.

The GICP_IRQCR characteristics are:

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all GIC-600 configurations.
AttributesSee GICP register summary.

The following figure shows the bit assignments.

Figure 4-56 GICP_IRQCR bit assignments


The following table shows the bit assignments.

Table 4-72 GICP_IRQCR bit assignments

Bits Name Function
[31:10] - Reserved, RAZ.
[9:0] SPIID

SPI ID.

Returns 0 if an invalid entry is written.

Creates a level-triggered interrupt if it is owned on chip. Otherwise it behaves as a normal message-based SPI.

In a multichip configuration, the SPIID field must only be programmed to an SPI ID that the chip owns. The relevant GICD_CHIPRn register controls the SPI ownership.

Arm® recommends that if these registers are used, then the SPI must not be used for another device either with a wire or as a message-based interrupt.

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