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Interrupt Contribution Enable Clear Register 0, GICP_INTENCLR0

This register contains the clear mechanism for the counter interrupt contribution enables. The GIC-600 supports five counters, n = 0-4.

The GICP_INTENCLR0 characteristics are:

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all GIC-600 configurations.
AttributesSee GICP register summary.

The following figure shows the bit assignments.

Figure 4-50 GICP_INTENCLR0 bit assignments

The following table shows the bit assignments.

Table 4-66 GICP_INTENCLR0 bit assignments

Bits Name Function
[31:5] - Reserved, RAZ.
[4:0] INTEN

Interrupt enable. The INTEN[n] bit is the interrupt disable for counter n. This field resets to an unknown value.

Writing 1 to a bit location clears the interrupt enable for the associated counter.

Writing 0 to a bit location has no effect. To enable a counter interrupt enable, use the GICP_INTENSET0 register.

Reads return the state of the interrupt enables.

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