Overflow Status Set Register 0, GICP_OVSSET0
This register provides the set mechanism for the counter overflow status bits and provides read access to the counter overflow status bit values. The GIC-600 supports five counters, n = 0-4.
The GICP_OVSSET0 characteristics are:
|Usage constraints||There are no usage constraints.|
|Configurations||Available in all GIC-600 configurations.|
|Attributes||See GICP register summary.|
The following figure shows the bit assignments.
Figure 4-52 GICP_OVSSET0 bit assignments
The following table shows the bit assignments.
Table 4-68 GICP_OVSSET0 bit assignments
Overflow status. The OVS[n] bit is the overflow set for counter n. This field resets to zero.
Writing 1 to a bit location sets the overflow status for the associated counter.
Writing 0 to a bit location has no effect. To clear a counter overflow status, use the GICP_OVSCLR0 register.
Reads return the state of the overflow status bits.
When the agent controlling the GIC-600 sets an OVS bit, it is similar to an OVS bit being set because of a counter overflow. However, it is implementation defined whether the overflow triggers the PMU interrupt or performs a capture of the PMU counter values.
Setting the OVS bit triggers the overflow interrupt if it is enabled.