Error Interrupt Configuration Registers, GICT_ERRIRQCR<n>
GICT_ERRIRQCR0 controls the fault handling interrupts. GICT_ERRIRQCR1 controls the error recovery interrupts.
The GICT_ERRIRQCR<n> characteristics are:
|Usage constraints||If GICD_SAC.GICTNS == 0, then only Secure software can access the functions of this register.|
|Configurations||Available in all GIC-600 configurations.|
|Attributes||See GICT register summary.|
The following figure shows the bit assignments.
Figure 4-41 GICT_ERRIRQCR<n> bit assignments
The following table shows the bit assignments.
Table 4-54 GICT_ERRIRQCR<n> bit assignments
Returns 0 if an invalid entry is written.
In a multichip configuration, the SPIID field must only be programmed to an SPI ID that the chip owns. The relevant GICD_CHIPRn register controls the SPI ownership.
Arm® recommends that if these registers are used, then the SPI must not be used for another device either with a wire or as a message-based interrupt.