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Revisions

This appendix describes changes between released issues of this book.

Table C-1 Issue 0000-00

Change Location Affects
First release - -

Table C-2 Differences between issue 0000-00 and issue 0000-01

Change Location Affects
Added note About the GIC-600 r0p0
Added note Top level r0p0
Updated section Features r0p0
Updated section Distributor AXI4-Stream interfaces r0p0
Updated section Distributor ACE-Lite slave interface r0p0
Updated section Distributor ACE-Lite master interface r0p0
Updated section Distributor Q-Channels r0p0
Updated table Table   2-6 Configurable options for the Distributor r0p0
Updated section Redistributor GIC Stream protocol interface r0p0
Updated section Redistributor Q-Channel r0p0
Updated table Table   2-8 Redistributor miscellaneous input signals r0p0
Updated section ITS ACE-Lite slave interface r0p0
Updated section ITS AXI4-Stream interface r0p0
Updated table Table   2-11 ITS miscellaneous signals r0p0
Updated table Table   2-12 Configurable options for the ITS r0p0
Updated section MSI-64 ACE-Lite interfaces r0p0
Updated table Table   2-14 MSI-64 miscellaneous signals r0p0
Updated table Table   2-15 Configurable options for the MSI-64 Encapsulator r0p0
Updated section SPI Collator wires r0p0
Updated section Wake Request miscellaneous signals r0p0
Updated section Wake Request configuration r0p0
Updated section Interconnect configuration r0p0
Changed note LPIs r0p0
Updated section Choosing between LPIs and SPIs r0p0
Updated section Physical interrupt signals (PPIs and SPIs) r0p0
Updated section Affinity routing and assignment r0p0
Added section 1 of N SPI interrupt selection r0p0
Updated section Backwards compatibility r0p0
Updated section LPI caching r0p0
Updated section Memory access and attributes r0p0
Updated section MSI-64 r0p0
Updated section RAM r0p0
Updated section Performance Monitoring Unit r0p0
Updated table Table   3-6 ECC error reporting r0p0
Updated section About the GIC-600 r0p0
Added section Register map pages r0p0
Updated section GIC-600 register access and banking r0p0
Updated table Table   4-2 Distributor registers (GICD/GICDA) summary r0p0
Updated table Table   4-4 GICD_TYPER bit assignments r0p0
Updated table Table   4-6 GICD_FCTLR bit assignments r0p0
Updated table Table   4-8 GICD_SAC bit assignments r0p0
Updated table Table   4-20 Distributor registers (GICA) for message-based SPIs summary r0p0
Updated table Table   4-21 Redistributor registers for control and physical LPIs summary r0p0
Updated table Table   4-22 GICR_IIDR bit assignments r0p0
Updated table Table   4-23 GICR_TYPER bit assignments r0p0
Updated table Table   4-25 GICR_FCTLR bit assignments r0p0
Updated table Table   4-26 GICR_PWRR bit assignments r0p0
Updated table Table   4-30 GICR_MISCSTATUSR bit assignments r0p0
Updated table Table   4-34 GICR_CFGID1 bit assignments r0p0
Updated table Table   4-35 ITS control register summary r0p0
Updated table Table   4-39 GITS_OPR bit assignments r0p0
Updated table Table   4-44 GICT register summary r0p0
Updated table Table   4-47 GICT_ERR<n>CTLR bit assignments r0p0
Updated table Table   4-48 GICT_ERR<n>STATUS bit assignments r0p0
Updated table Table   4-50 GICT_ERR<n>MISC0 bit assignments r0p0
Updated table Table   4-51 Data field encoding r0p0
Added section Peripheral ID2 Register, GICT_PIDR2 r0p0
Updated table Table   4-57 GICP register summary r0p0
Updated table Table   4-59 GICP_EVTYPERn bit assignments r0p0
Updated table Table   4-60 EVENT field encoding r0p0
Updated table Table   4-63 GICP_CNTENSET0 bit assignments r0p0
Updated table Table   4-64 GICP_CNTENCLR0 bit assignments r0p0
Updated table Table   4-65 GICP_INTENSET0 bit assignments r0p0
Added section Peripheral ID2 Register, GICP_PIDR2 r0p0
Updated section Power control signals r0p0
Updated section Interrupt signals r0p0
Updated section CPU interface signals r0p0
Updated section Interblock signals r0p0
Updated section Implementation-defined features reference r0p0

Table C-3 Differences between issue 0000-01 and issue 0002-00

Change Location Affects
Updated fourth paragraph About the GIC-600 All releases
Updated section Components All releases
Updated section Compliance All releases
Updated section Features All releases
Updated Figure Figure   2-1 GIC-600 Distributor All releases
Updated section Distributor AXI4-Stream interfaces All releases
Updated section Distributor ACE-Lite slave interface All releases
Updated section Distributor ACE-Lite master interface All releases
Updated section Distributor Q-Channels All releases
Updated table Distributor miscellaneous signals All releases
Updated table Table   2-6 Configurable options for the Distributor All releases
Updated section Redistributor All releases
Updated section Redistributor GIC Stream protocol interface All releases
Added table Table   2-7 GIC Stream protocol interface signals All releases
Updated section Redistributor PPI signals All releases
Updated section Redistributor miscellaneous input signals All releases
Updated section ITS All releases
Updated section ITS ACE-Lite slave interface All releases
Updated section ITS Q-Channel All releases
Updated table Table   2-11 ITS miscellaneous signals All releases
Updated section MSI-64 Encapsulator All releases
Updated section MSI-64 miscellaneous signals All releases
Updated section MSI-64 Encapsulator configuration All releases
Updated section SPI Collator All releases
Updated section SPI Collator AXI4-Stream interface All releases
Updated section SPI Collator wires All releases
Updated section SPI Collator power Q-Channel All releases
Updated section Wake Request All releases
Updated section Wake Request configuration All releases
Updated figure Figure   2-8 GIC-600 top-level structure options All releases
Renamed chapter 3 Operation All releases
Updated section SGIs All releases
Updated section PPIs All releases
Updated section SPIs All releases
Updated section LPIs All releases
Updated section Interrupt groups All releases
Updated section Physical interrupt signals (PPIs and SPIs) All releases
Updated section Affinity routing and assignment All releases
Updated section 1 of N SPI interrupt selection All releases
Updated section Power management All releases
Updated section Security All releases
Updated section Backwards compatibility All releases
Updated section Interrupt translation service (ITS) All releases
Updated section Memory access and attributes All releases
Updated table headings Table   3-5 Cacheability values All releases
Updated section MSI-64 All releases
Updated section RAM All releases
Updated section Reliability, Accessibility, and Serviceability All releases
Updated section Discovery All releases
Updated section Distributor registers (GICD/GICDA) summary All releases
Updated section Interrupt Class Registers, GICD_ICLARn All releases
Updated table Table   4-33 GICR_CFGID0 bit assignments All releases
Updated table Table   4-34 GICR_CFGID1 bit assignments All releases
Updated table Table   4-38 GITS_FCTLR bit assignments All releases
Updated section Operation Status Register, GITS_OPSR All releases
Updated table Table   4-40 GITS_OPSR bit assignments All releases
Updated section ITS translation register summary All releases
Updated table Table   4-48 GICT_ERR<n>STATUS bit assignments All releases
Updated section Error Record Address Register, GICT_ERR<n>ADDR All releases
Updated section Error Record Miscellaneous Register 0, GICT_ERR<n>MISC0 All releases
Updated table Table   4-50 GICT_ERR<n>MISC0 bit assignments All releases
Updated table Table   4-51 Data field encoding All releases
Updated section Error Record Miscellaneous Register 1, GICT_ERR<n>MISC1 All releases
Updated table Table   4-52 GICT_ERR10MISC1 bit assignments All releases
Updated section Event Type Configuration Registers, GICP_EVTYPERn All releases
Updated tables Table   4-59 GICP_EVTYPERn bit assignments and Table   4-60 EVENT field encoding All releases
Updated section Power control signals All releases
Updated section CPU interface signals All releases
Updated section ACE interface signals All releases
Updated section Miscellaneous signals All releases
Updated section Interblock signals All releases
Added section Interdomain signals All releases
Updated section Implementation-defined features reference All releases

Table C-4 Differences between issue 0002-00 and issue 0002-01

Change Location Affects
No technical changes - -

Table C-5 Differences between issue 0002-01 and issue 0003-00

Change Location Affects
Updated note about microarchitecture, and references to multichip About the GIC-600 r0p<n>
Updated note and tables Note, Table   2-1 AXI4-Stream input interface descriptions, and Table   2-2 AXI4-Stream output interface descriptions. All releases
Updated section Distributor Q-Channels All releases
Updated note in table Table   2-8 Redistributor miscellaneous input signals All releases
Updated the range of cores downstream Redistributor configuration All releases
Updated text following table Table   2-10 ITS ACE-Lite slave interface acceptance capabilities All releases
Clarified text ITS ACE-Lite master interface All releases
Clarified text in all subsections SPI Collator All releases
Clarified text Wake Request All releases
Removed key requirements of the interconnect Interconnect All releases
Added information Backwards compatibility All releases
Added paragraph to introduction Memory access and attributes All releases
Clarified text Scrub All releases
Added information Error record classification All releases
Clarified text for ITS caches and SPI Table   3-6 ECC error reporting All releases
Records 5 and 6 changed to reserved Table   3-7 Error handling records All releases
Updated text for syndromes 0x18 and 0x19 Table   3-8 Software errors, record 0 All releases
Error record name changed ITS command and translation error records 13+ All releases
Updated text in column Offset[x:16] Table   4-1 Register map pages All releases
Added Architecture defined column and various text changes throughout table Table   4-2 Distributor registers (GICD/GICDA) summary All releases
Updated section Distributor Control Register, GICD_CTLR All releases
Updated section Function Control Register, GICD_FCTLR All releases
Added text to table Table   4-13 GICD_IERRRn bit assignments All releases
Added PEW field and updated SPIS function Table   4-14 GICD_CFGID bit assignments All releases
Added sections Peripheral ID4 register, GICD_PIDR4, Peripheral ID3 register, GICD_PIDR3, Peripheral ID0 register, GICD_PIDR0, Peripheral ID1 register, GICD_PIDR1 All releases
Added columns Architecture defined, and Width Table   4-20 Distributor registers (GICA) for message-based SPIs summary All releases
Added Architecture defined column Table   4-21 Redistributor registers for control and physical LPIs summary, Table   4-29 Redistributor registers for SGIs and PPIs summary, and Table   4-35 ITS control register summary All releases
Updated descriptions of bits UEE, CEE, and LTE Table   4-38 GITS_FCTLR bit assignments All releases
Updated section Configuration ID Register, GITS_CFGID All releases
Added Architecture defined column ITS translation register summary, and Table   4-44 GICT register summary All releases
Records 5 and 6 changed to reserved Table   4-45 Error records All releases
Added information fields CE, IERR, SERR Table   4-48 GICT_ERR<n>STATUS bit assignments All releases
Updated text at syndromes 0x4 and 0x19 Table   4-51 Data field encoding All releases
Added section Error Group Status Register, GICT_ERRGSR All releases
Added Architecture defined column, and registers GICP_IRQCR, GICP_PMAUTHSTATUS, and GICP_PMDEVARCH Table   4-57 GICP register summary All releases
Added section Interrupt Configuration Register, GICP_IRQCR All releases
Corrected signal names CPU interface signals All releases
Clarified introduction text Implementation-defined features All releases

Table C-6 Differences between issue 0003-00 and issue 0102-00

Change Location Affects
Updated section, Distributor Distributor r1p2
Added figures Figure   1-1 GIC-600 with free-flowing interconnect in an example system, Figure   1-2 GIC-600 with interconnect in an example system, and Figure   1-3 Monolithic GIC-600 with interconnect in an example system r1p2
Added note following Figure 1-2 Top level r1p2
Updated paragraph following Figure 1-3 Top level All releases
Added bullet point Registers and programming r1p2
Updated section Error correction All releases
Updated section Product revisions r1p2
Updated note and tables Note, Table   2-1 AXI4-Stream input interface descriptions, and Table   2-2 AXI4-Stream output interface descriptions. All releases
Updated paragraph following Table Table   2-3 Distributor ACE-Lite slave interface acceptance capabilities All releases
Updated Note Distributor ACE-Lite master interface All releases
Updated section Distributor Q-Channels All releases
Added section P-Channel r1p2
Updated table Table   2-6 Configurable options for the Distributor r1p2
Updated table Table   2-8 Redistributor miscellaneous input signals All releases
Updated table Redistributor configuration All releases
Updated table for combined acceptance capability attribute, write acceptance capability, and updated text following table Table   2-10 ITS ACE-Lite slave interface acceptance capabilities All releases
Updated section ITS ACE-Lite master interface All releases
Updated section SPI Collator All releases
Updated section SPI Collator AXI4-Stream interface All releases
Updated section and changed section title from SPI Collator Q-Channel SPI Collator power Q-Channel All releases
Updated table SPI Collator configuration r1p2
Updated section SPI Collator clock Q-Channel All releases
Updated section Wake Request All releases
Deleted key requirements of the interconnect Interconnect All releases
Added text to section Hierarchy All releases
Updated introduction PPIs All releases
Updated section SPIs All releases
Updated section Backwards compatibility All releases
Added paragraph to introduction Memory access and attributes All releases
Updated first sentence to subsection "Snapshot" Snapshot All releases
Updated introduction Reliability, Accessibility, and Serviceability All releases
Updated section Scrub All releases
Updated section Error record classification All releases
Added Target cache to table Table   3-6 ECC error reporting All releases
Updated records 5 and 6 Table   3-7 Error handling records All releases
Updated cells 0x18 and 0x19 Table   3-8 Software errors, record 0 All releases
Updated name of error record, and added text to introduction ITS command and translation error records 13+ All releases
Added section for multichip operation Multichip operation r1p2
Updated table Table   4-1 Register map pages All releases
Updated table Table   4-2 Distributor registers (GICD/GICDA) summary All releases
Updated section Distributor Control Register, GICD_CTLR All releases
Updated section Function Control Register, GICD_FCTLR All releases
Added section Chip Status Register, GICD_CHIPSR r1p2
Added section Default Chip Register, GICD_DCHIPR r1p2
Added section Chip Registers, GICD_CHIPR<n> r1p2
Updated table Table   4-13 GICD_IERRRn bit assignments All releases
Added bitfield PEW Table   4-14 GICD_CFGID bit assignments All releases
Added sections Peripheral ID4 register, GICD_PIDR4, Peripheral ID3 register, GICD_PIDR3, Peripheral ID0 register, GICD_PIDR0, Peripheral ID1 register, GICD_PIDR1 All releases
Updated table Table   4-20 Distributor registers (GICA) for message-based SPIs summary All releases
Updated table Table   4-21 Redistributor registers for control and physical LPIs summary All releases
Added note to bitfield CGO function description Table   4-25 GICR_FCTLR bit assignments All releases
Updated table Table   4-29 Redistributor registers for SGIs and PPIs summary All releases
Updated table Table   4-35 ITS control register summary All releases
Updated descriptions of bits LTE, UEE, CEE, and CGO Table   4-38 GITS_FCTLR bit assignments All releases
Updated section Configuration ID Register, GITS_CFGID All releases
Updated table ITS translation register summary All releases
Updated table Table   4-44 GICT register summary All releases
Updated table Table   4-45 Error records All releases
Updated table Table   4-48 GICT_ERR<n>STATUS bit assignments All releases
Updated table Table   4-51 Data field encoding All releases
Added section Error Group Status Register, GICT_ERRGSR All releases
Added section Error Interrupt Configuration Registers, GICT_ERRIRQCR<n> All releases
Updated table Table   4-57 GICP register summary All releases
Added section Interrupt Configuration Register, GICP_IRQCR All releases
Added power P-Channel signals preq, pstate, paccept, pdeny, pactive Power control signals r1p2
Updated signal names CPU interface signals All releases
Added signals icdptdest, icdptkeep, icpdtid, icpdtkeep, icditdest, icditkeep, icidtdid, icidtkeep, iccdtdest, and iccdtid. Interblock signals All releases
Added section for interchip signals Interchip signals r1p2
Updated introduction Implementation-defined features All releases

Table C-7 Differences between issue 0102-00 and issue 0103-00

Change Location Affects
Added pseudocode Redistributor power management All revisions
Added information about single operation of the Routing table About multichip operation All revisions
Updated the procedure Connecting the chips All revisions
Updated the description SPI ownership All revisions
Added information about the Routing table during power up. Isolating a chip from the system All revisions
Added an r1p3 entry to the Version field description. Table   4-34 GICR_CFGID1 bit assignments r1p3
Corrected the UE bit description Table   4-47 GICT_ERR<n>CTLR bit assignments All revisions
Added what function GICT_ERRIRQCR0 controls. Updated the SPIID description. Error Interrupt Configuration Registers, GICT_ERRIRQCR<n> All revisions
Corrected the description of the ACC event Table   4-60 EVENT field encoding All revisions
Updated the SPIID description. Interrupt Configuration Register, GICP_IRQCR All revisions

Table C-8 Differences between issue 0103-00 and issue 0104-00

Change Location Affects
Added reference to Arm®AMBA® AXI and ACE Protocol Specification Distributor AXI4-Stream interfaces All releases.
Updated range of affinity0 Distributor configuration All releases.
Number of cores updated to 1-64. Redistributor GIC Stream protocol interface All releases.

Note before figure replaced by two paragraphs. Instructions changed.

GITS_FCTLR,ACELM_DIS changed to GITS_FDCTLR_DMA.
ITS All releases.
Updated target_address[<n>ADDR_WIDTH-17:0]. ITS ACE-Lite slave interface

ITS miscellaneous signals

All releases.
Updated ranges of EventId and DeviceID. ITS configuration All releases.
Updated description of msi64_translator_page.s MSI-64 miscellaneous signals All releases.
Changed note. MSI-64 All releases.
Changed procedure. Connecting the chips r1p2 and later.
Changed note. SPI ownership r1p2 and later.
Changed descriptions of GICR_TYPER bit assignments. Interrupt Controller Type Register, GICR_TYPER All releases.
Clarified the uncorrectable error recovery sequence. All releases.
Changed table. Register map pages All releases.
Updated Distributor control register. Distributor Implementer Identification Register, GICD_IIDR All releases.
Updated Implementation ID register. Redistributor Implementation Identification Register, GICR_IIDR All releases.
Updated Configuration ID1 register. Configuration ID1 Register, GICR_CFGID1 All releases.
Added values for bit [11]. Function Control Register, GITS_FCTLR All releases.
Updated values for IERR and SERR. Error Record Primary Status Register, GICT_ERR<n>STATUS All releases.
Updated value of record 13+. Error Record Miscellaneous Register 0, GICT_ERR<n>MISC0, All releases.

Added signals to table.

Changed awuser_[its[_<num>]]_s[did_width:0] to awuser_[its[_<num>]]_s[variable:0].

ACE interface signals All releases.

Table C-9 Differences between issue 0104-00 and issue 0106-00

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