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Components

The GIC-600 comprises several significant blocks that work in combination to create a single architecturally compliant GICv3 implementation within the system. The GIC-600 top level can have one of several optional structures.

The GIC-600 consists of the following blocks:

Distributor

The Distributor is the hub of all the GIC communications and contains the functionality for all Shared Peripheral Interrupts (SPIs) and Locality-specific Peripheral Interrupts (LPIs). It is responsible for the entire GIC programmers model, except for the GITS_TRANSLATER register, which is hosted in the Interrupt Translation Service (ITS) block.

The Distributor also maintains the coherency of the SPI register space in multichip configurations.

Note

The LPI functionality for all cores on a chip is combined into a single cache in the Distributor.
Redistributor

The Redistributor maintains the Private Peripheral Interrupts (PPIs) and Software Generated Interrupts (SGIs) for a particular set of cores. A Redistributor can scale from 1-64 cores and is best placed next to the processors that it is servicing to reduce wiring to the cores.

A Redistributor is also referred to as a PPI block.

The GICv3 architecture specifies a Redistributor address space containing two pages per core. The SGI page functionality is contained in the GIC-600 Redistributor. However, the command and control pages for all cores on a chip are contained in the Distributor.

The GIC-600 supports powering down the Redistributors and the associated cores.

Interrupt Translation Service

The ITS translates message-based interrupts, Message-Signaled Interrupts (MSI/MSIx), from an external PCI Express (PCIe) Root Complex (RC), or other sources. The ITS also manages LPIs during core power management.

The GIC-600 supports up to 16 ITS blocks per chip.

For more information about the ITS, see the Arm® GICv3 and GICv4 Software Overview.

MSI-64 Encapsulator

The MSI-64 Encapsulator is a small block that combines the DeviceID (DID), required by writes to the GITS_TRANSLATER register, into a single memory access.

SPI Collator

The GIC-600 supports up to 960 SPIs that are spread across the system. The SPI Collator enables SPIs to be converted into messages remotely from the Distributor. This enables hierarchical clock gating of the Distributor and the use of other more aggressive low-power states.

Wake Request

The Wake Request contains all the architecturally defined wake_request signals for each core on the chip. It is a separate block that can be positioned remotely from the Distributor, such as next to a system control processor if necessary.

GIC interconnect

The GIC interconnect is a set of components that can be used for routing the AXI4-Stream interfaces between the different blocks.

Top level

The top level has no specific interfaces but combines the interfaces of other blocks within the clock or power domain to reduce the number of domain bridges. The GIC-600 build scripts enable you to build the GIC from a single combined block or a set of individual blocks that are interconnected using your own transport layer.

These blocks can be combined in different ways:

  • In systems where there is an available free-flowing transport layer in place, existing buses can be used to route the GIC traffic.
  • The GIC-600 includes a narrow, 16-bit, AXI4-Stream interconnect that can be used for routing internal traffic.

The following figure shows a GIC-600 with a free-flowing interconnect in an example system.

Figure 1-1 GIC-600 with free-flowing interconnect in an example system


Note

A free-flowing channel is clear to transmit a transaction that arrives at its destination without any non-transient dependencies on other transactions.

The following figure shows a GIC-600 with interconnect in an example system.

Figure 1-2 GIC-600 with interconnect in an example system


Note

Cross-chip interfaces enable communication between cores in a multichip configuration. Cross-chip is supported in product version r1p2 onwards.

The following figure shows a monolithic GIC-600 with interconnect in an example system.

Figure 1-3 Monolithic GIC-600 with interconnect in an example system


Note

If the GIC supports LPIs, there must be free-flowing access to main memory. This requirement is irrespective of the interconnect that is used for routing the AXI4-Stream interfaces. For more information, see the Arm®CoreLink™ GIC‑600 Generic Interrupt Controller Configuration and Integration Manual.

The GIC-600 supports cores that implement only the ARMv8.0-A architecture, and later versions such as v8.2-A. The cores must also support the GIC CPU interface with the standard GIC AXI4-Stream protocol interface. The GIC-600 implements version 3.0 of the Arm® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0.

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