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1 of N SPI interrupt selection

The GIC-600 supports 1 of N selection of SPI interrupts.

When the relevant GICD_IROUTERn.Interrupt_Routing_Mode == 1, the GIC selects the appropriate core for a SPI.

When GICD_IROUTERn.Interrupt_Routing_Mode == 0, the SPI is routed to the core specified by the remaining fields of GICD_IROUTERn.

The selections that the GIC-600 makes can be controlled or influenced by several 1 of N features:

cpu_active
A cpu_active signal is an input to a Redistributor that corresponds to a particular core. It indicates to the GIC that a core is in a transparent low-power state, such as retention, and that it must be selected as a target for a SPI if there are no other options possible.
Typically, a power controller or power control logic generates the cpu_active signal. If this signal is not available in the system, the input must be tied HIGH.

Note

The cpu_active provides an indication only, it cannot stop selection of the core or stop the GIC sending messages to the core.
GICR_CTLR.DPGxx (Disabled Processor Group)
Setting a DPG bit prevents 1 of N interrupts of a particular group being sent to that core. Any interrupts that have not reached a core at the time of the change are recalled and reprioritized by the GIC. For information about the DPG bits, see GICR_CTLR, Redistributor Control Register in the Arm® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0.
Processor and GICD Group enables and GICR_WAKER.ProcessorSleep
A 1 of N interrupt is not sent to a core if the core is asleep as indicated by GICR_WAKER.ProcessorSleep, or the interrupt group is disabled by either the processor, or the GICD_CTLR group.
Interrupt class
This is an implementation-defined feature that the GIC-600 provides. Each core can be assigned to either class 0 or class 1 by writing to the relevant GICR_CLASS register. A SPI, programmed as 1 of N, by GICD_IROUTERn.Interrupt_Routing_Mode, can be programmed to target either class 0, class 1, or both classes by the GICD_ICLARn register. By default, all 1 of N SPIs can go to both classes, so the interrupt class feature is disabled by default. The system can use this partitioning for any purpose, for example in a big.LITTLE™ system, all the big cores can be in class 1 and little cores in class 0, allowing 1 of N SPIs to be partitioned according to the amount of processing they require.
GICD_CTLR.E1NWF
The GICD_CTLR register E1NWF bit controls whether the GIC-600 wakes a core if there are no other possible targets for a 1 of N SPI.
The GIC tries to wake the minimum of cores possible and only wakes a core if there is no other possible target awake that is able to accept the 1 of N interrupt. To do this, the GIC uses the GICR.DPG and GICR_CLASS.Class bits to determine if any core is awake that can accept the interrupt. If a suitable core is not awake, the GIC then wakes a core.
Arm strongly recommends that if you use GICD_CTLR.E1NWF, you must also set the DPGx bits of register GICR_CTLR to specify whether a core is likely to accept a particular interrupt group in a timely manner. The GIC does not continue to wake cores until one is found. The GIC-600 uses two passes to try to find the best place for a 1 of N interrupt, by using a round-robin arbiter between:
  • Any core that has cpu_active set, is fully enabled for the interrupt, and has no other pending interrupts.
  • Any core that is fully enabled for the interrupt and has no interrupts of a higher priority than the 1 of N interrupt.

If neither option is available to the 1 of N, the interrupt is assigned to any legal target and regularly re-evaluated to ensure that it is not excluded from other SPIs of the same priority.

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