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ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1

The AArch64 register ID_ISAR5_EL1 provides information about the instructions implemented in AArch32 state, including the instructions provided by the optional Cryptographic Extension.

Bit field descriptions

ID_ISAR5_EL1 is a 32-bit register.

Figure 2-2 ID_ISAR5_EL1 bit assignments


[31:28]
res0Reserved.
RDM, [27:24]

Indicates whether RDM instructions are implemented. The value is:

0x1SQRDMLAH and SQRDMLSH instructions are implemented.
[23:20]
res0Reserved.
CRC32, [19:16]

Indicates whether CRC32 instructions are implemented in AArch32 state. The value is:

0x1CRC32 instructions are implemented.
SHA2, [15:12]

Indicates whether SHA2 instructions are implemented in AArch32 state. The possible values are:

0x0Cryptographic Extension is not implemented or is disabled.
0x1SHA256H, SHA256H2, SHA256SU0, and SHA256SU1 instructions are implemented.
SHA1, [11:8]

Indicates whether SHA1 instructions are implemented in AArch32 state. The possible values are:

0x0Cryptographic Extension is not implemented or is disabled.
0x1SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, and SHA1SU1 instructions are implemented.
AES, [7:4]

Indicates whether AES instructions are implemented in AArch32 state. The possible values are:

0x0Cryptographic Extension is not implemented or is disabled.
0x2AESE, AESD, AESMC, and AESIMC are implemented, plus PMULL and PMULL2 instructions operating on 64-bit data.
SEVL, [3:0]

Indicates whether the SEVL instruction is implemented. The value is:

0x1SEVL implemented to send event local.
Configurations
This register has no configuration options.

Usage constraints

Accessing the ID_ISAR5_EL1

To access the ID_ISAR5_EL1:

MRS <Xt>, ID_ISAR5_EL1 ; Read ID_ISAR5_EL1 into Xt

Register access is encoded as follows:

Table 2-3 ID_ISAR5_EL1 access encoding

op0 op1 CRn CRm op2
11 000 0000 0010 101
Accessibility
This register is accessible as follows:
EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- RO RO RO RO RO
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