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Arm Cortex-A55 Core Technical Reference Manual : About the Generic Interrupt Controller CPU Interface

About the Generic Interrupt Controller CPU Interface

The GIC CPU Interface, when integrated with an external distributor component, is a resource for supporting and managing interrupts in a cluster system.

The GIC CPU interface hosts registers to mask, identify, and control states of interrupts forwarded to that core. There is a separate GIC CPU interface for each core in the system.

The Cortex®-A55 core implements the GIC CPU interface as described in the Arm® Generic Interrupt Controller Architecture Specification. This interfaces with an external GICv3 or GICv4 interrupt distributor component within the system.

Note

This chapter describes only features that are specific to the Cortex-A55 core implementation. Additional information specific to the DSU can be found in Arm® DynamIQ™ Shared Unit Technical Reference Manual.

The GICv4 architecture supports:

  • Two security states.
  • Interrupt virtualization.
  • Software-generated Interrupts (SGIs).
  • Message Based Interrupts.
  • System register access for the CPU interface.
  • Interrupt masking and prioritization.
  • Cluster environments, including systems that contain more than eight cores.
  • Wake-up events in power management environments.

The GIC includes interrupt grouping functionality that supports:

  • Configuring each interrupt to belong to an interrupt group.
  • Signaling Group 1 interrupts to the target core using either the IRQ or the FIQ exception request.
  • Signaling Group 0 interrupts to the target core using the FIQ exception request only.
  • A unified scheme for handling the priority of Group 0 and Group 1 interrupts.

This chapter describes only features that are specific to the Cortex-A55 core implementation.