The Cortex®-A55 core is designed to be the Little core in a big.LITTLE™ arrangement and is fully compatible with the big.LITTLE use models introduced by previous generations of Cortex cores.
The Cortex-A55 core includes the following features:
- Full implementation of the Arm®v8.2‑A A64, A32, and T32 instruction sets.
- Both the AArch32 and AArch64 execution states at all Exception levels (EL0 to EL3).
- In-order pipeline with direct and indirect branch prediction.
- Separate L1 data and instruction side memory systems with a Memory Management Unit (MMU).
- Support for Arm TrustZone® technology.
- Optional Data Engine unit that implements the Advanced SIMD and floating-point architecture support.
- Optional Cryptographic Extension. This architectural extension is only available if the Data Engine is present.
- Generic Interrupt Controller (GIC) CPU interface to connect to an external distributor.
- Generic Timers interface supporting 64-bit count input from an external system counter.
- Optional unified private L2 cache.
L1 and L2 cache protection in the form of Error Correction Code (ECC) or parity on all RAM instances.
- Reliability, Availability, and Serviceability (RAS) Extension.
- Armv8.2‑A debug logic.
- Performance Monitoring Unit (PMU).
- Embedded Trace Macrocell (ETM) that supports instruction trace only.