The Cortex®-A55 core is highly configurable.
Build-time configuration options make it possible to meet functional requirements with the smallest possible area and power. In a configuration with more than one core, all cores have the same build-time configuration except for the L2 cache inclusion and size.
The following table lists the implementation options for a core.
Table A1-1 Implementation options for a core
|Feature||Range of options||Notes|
|L1 instruction cache size||
|L1 data cache size||
|L2 cache size||
|ECC or parity core cache protection||
||Not available if the L3 cache is implemented without L3 cache protection.|
|Advanced SIMD and floating-point support||
||There is no option to implement floating-point without Advanced SIMD.|
||There is no option to implement the Cryptographic Extension without the Advanced SIMD and floating-point support.|
|CoreSight Embedded Logic Analyzer (ELA)||
||Support for integrating CoreSight ELA-500. The CoreSight ELA-500 is a separately licensable product.|
|CoreSight ELA RAM address size||2-25||See the Arm® CoreSight™ ELA-500 Embedded Logic Analyzer Technical Reference Manual for more details about the RAM sizing.|
|Dot Product instruction support||
||Support for the Armv8.4‑A SDOT and UDOT instructions. There is no option to implement the Dot Product instructions without the Advanced SIMD and floating point support.|