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Arm Cortex-A55 Core Technical Reference Manual : Data cache coherency

Data cache coherency

The Cortex®-A55 core uses the MESI protocol to maintain data coherency between multiple cores.

MESI describes the state that a shareable line in a L1 data cache can be in:

MModified/UniqueDirty (UD). The line is in only this cache and is dirty.
EExclusive/UniqueClean (UC). The line is in only this cache and is clean.
SShared/SharedClean (SC). The line is possibly in more than one cache and is clean.
IInvalid/Invalid (I). The line is not in this cache.

The DCU stores the MESI state of the cache line in the tag and dirty RAMs.

Note

The names UniqueDirty, SharedDirty, UniqueClean, SharedClean, and Invalid are the AMBA names for the cache states. The Cortex-A55 core does not use the SharedDirty AMBA state.