Data cache disabled behavior
If the SCTLR.C bit is set to 0, load and store instructions do not access any of the L1 data, L2, or DSU L3 caches.
The SCTLR.C bit controls whether accesses from the core can look up and allocate into the data cache and unified L2 or L3 caches. Data cache maintenance operations execute normally, regardless of how the SCTLR.C bit is set.
If the SCTLR.C bit is set to 0, then the following apply:
- Instruction fetches cannot allocate in the L2 or L3 caches.
- All load and store instructions to cacheable memory are treated as if they were non-cacheable. Therefore, they are not coherent with the caches in this core or the caches in other cores, and software must take this into account.
The L2 and L1 data caches cannot be disabled independently.