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Arm Cortex-A55 Core Technical Reference Manual : Instruction cache disabled behavior

Instruction cache disabled behavior

If the instruction cache is disabled, all instruction fetches to cacheable memory are treated as if they were non-cacheable.

This means that instruction fetches might not be coherent with caches in other cores, and software must take account of this.

  • In AArch64 state, lines may still be allocated into the instruction cache even if the memory is marked non-cacheable or the instruction cache is disabled. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.
  • In AArch32 state, lines are not allocated into instruction cache when the instruction cache is disabled. Allocation into the instruction cache only occurs when the instruction cache is enabled, and memory is marked as Write-Back or Write-Through cacheable.