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Arm Cortex-A55 Core Technical Reference Manual : Instruction cache speculative memory accesses

Instruction cache speculative memory accesses

Instruction fetches are speculative, as there can be several unresolved branches in the pipeline. There is no execution guarantee.

A branch instruction or exception in the code stream can cause a pipeline flush, discarding the currently fetched instructions. On instruction fetch accesses, pages with Device memory type attributes are treated as Non-Cacheable Normal Memory.

Device memory pages must be marked with the translation table descriptor attribute bit Execute Never (XN). The device and code address spaces must be separated in the physical memory map. This separation prevents speculative fetches to read-sensitive devices when address translation is disabled.

If the instruction cache is enabled, and if the instruction fetches miss in the L1 instruction cache, they can still look up in the L1 data caches. However, a new line is not allocated in the data cache unless the data cache is enabled.

See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.