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Arm Cortex-A55 Core Technical Reference Manual : Write Streaming Mode

Write Streaming Mode

A cache line is allocated to the L1 on either a read miss or a write miss.

However, there are some situations where allocating on writes is not required. For example, when executing the C standard library memset() function to clear a large block of memory to a known value. Writes of large blocks of data can pollute the cache with unnecessary data. It can also waste power and performance if a linefill must be performed only to discard the linefill data because the entire line was subsequently written by the memset().

To counter this, the BIU includes logic to detect when the core has written a full cache line before the linefill completes. If this situation is detected on a configurable number of consecutive linefills, then it switches into write streaming mode. This is sometimes referred to as read allocate mode.

When in write streaming mode, loads will behave as normal, and can still cause linefills, and writes will still lookup in the cache, but if they miss then they will write out to L2 (or possibly L3) rather than starting a linefill.

Note

More than the specified number of linefills might be observed on the ACE or CHI master interface, before the BIU detects that three full cache lines have been written and switches to write streaming mode.

The BIU continues in write streaming mode until it detects either a cacheable write burst that is not a full cache line, or there is a load from the same line as is currently being written to L2.

When a CPU has dropped into write streaming mode, the BIU continues to monitor the bus traffic and will signal to the L2 for it to go into write streaming mode when a further number of full cache line writes are seen.

AArch64 state
CPUECTLR_EL1.L1WSCTL configures the L1 write streaming mode threshold, CPUECTLR_EL1.L2WSCTL configures the L2 write streaming mode threshold, and CPUECTLR_EL1.L3WSCTL configures the L3 write streaming mode threshold.
AArch32 state
CPUECTLR.L1WSCTL configures the L1 write streaming mode threshold, CPUECTLR.L2WSCTL configures the L2 write streaming mode threshold, and CPUECTLR.L3WSCTL configures the L3 write streaming mode threshold.