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Arm Cortex-A55 Core Technical Reference Manual : Encoding for tag and data in the L1 instruction cache

Encoding for tag and data in the L1 instruction cache

The L1 instruction cache is different from the L1 data cache. This is shown in the encodings and data format used in the cache debug operations that are used to access the tag and data memories.

The following table shows the encoding that is required to select a given cache line.

The set-index range parameter (S) is:

S=12For a 16KB cache.
S=13For a 32KB cache.
S=14For a 64KB cache.

Table A6-5 Cortex®-A55 Instruction Cache Tag and Data location encoding

Bit-field of Rd Description
[31:30] Cache Way
[29:S] Unused
[S-1:6] Set index
[5:2] Cache data element offset (Data Register only)
[1:0] Unused

The following table shows the tag, instruction, and valid data for the selected cache line using only Data Register.

Table A6-6 Cortex-A55 Instruction Cache Tag data format

Bit-field of Data Register 0 Description
[31] Unused
[30:29]

Valid and set mode:

0b00 A32
0b01 T32
0b10 A64
0b11 Invalid
[28] Non-secure state (NS) -
[27:0] Tag address -

The cache data RAMs store instructions in a pre-decoded format. Each A32 or A64 or 32-bit T32 instruction is expanded to 40-bits and each 16-bit T32 instruction occupies 20 bits of the cache. The L1 Instruction Cache Data Read Operation returns two 20-bit entries from the cache in Data Register 0 and Data Register 1. Each corresponds to the 16-bit aligned offset in the cache line:

Data Register 0[19:0]Pre-decode data from cache offset.
Data Register 1[19:0]Pre-decode data from cache offset +2.

In A32 or A64 state, these two combined fields always represent a single pre-decoded instruction. In T32 state, they can represent any combination of 16-bit and partial or full 32-bit instructions.