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Arm Cortex-A55 Core Technical Reference Manual : Walk cache descriptor fields

Walk cache descriptor fields

The following table shows the walk cache descriptor data fields for Tag and Data RAMs.

Table A6-11 Walk cache descriptor fields for Tag RAM

Field Bit Position Width Description
Valid [0] 1 Indicates that the entry is valid.
NS (walk) [1] 1 The Security state of the entry fetch.
ASID [17:2] 16 Address Space Identifier.
VMID [33:18] 16 Virtual Machine Identifier.
HYP/EL2 [34] 1 Set if the entry was fetched in HYP, EL2, or Virtual Host Extension (VHE) mode.
EL3 [35] 1 Set if the entry was fetched in AArch64 EL3 mode.
Arch [38:36] 3 Used to determine how many and which bits of address are used for constructing the physical address of the pagewalk.
Domain [42:39] 4 Valid only if the entry was fetched in VMSAv7 format.
Address Sign Bit [45] 1 Address sign bit, VA[48].
VA [69:46] 24 Virtual Address sign bit.
S2AP [71:70] 2 Stage 2 access permission.
S2level [73:72] 2 The stage 2 level which translates the IPA to PA for the page table entry.
Parity [81:80] 2 Parity Bits.

Table A6-12 Walk cache descriptor fields for Data RAM

Field Bit Position Width Description
APTable [1:0] 2 Combined ATable bits from stage 1 descriptors up to the last level.
XNTable [2] 1 Combined XNTAble bits from stage 1 descriptors up to the last level.
PXNTable [3] 1 Combined PXNTable bits from stage 1 descriptors up to the last level.
NSTable [4] 1 Combined NSTable bits from first and second-level stage 1 tables or NS descriptors (VMSA).
Attrs [12:5] 8 Physical address attributes of the final level stage 1 table.
PA [42:13] 30 Physical address of the stage 1 last translation level page table entry.
Parity [43] 1 Parity inclusion is core configuration dependent. If parity is no configured, these bits are absent.