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Arm Cortex-A55 Core Technical Reference Manual : L1 data memory system

L1 data memory system

The L1 data cache is organized as a Virtually Indexed Physically Tagged (VIPT) cache, with alias avoidance logic so that it appears to software as if it were physically indexed.

The Arm®v8‑A architecture does not support an operation to invalidate the entire data cache. If software requires this function, it must be constructed by iterating over the cache geometry and executing a series of individual invalidate by set/way instructions.