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Arm Cortex-A55 Core Technical Reference Manual : Internal exclusive monitor

Internal exclusive monitor

The Cortex®-A55 core L1 memory system has an internal exclusive monitor.

This monitor is a 2-state, open and exclusive, state machine that manages Load-Exclusive or Store-Exclusive accesses and Clear-Exclusive (CLREX) instructions. You can use these instructions to construct semaphores, ensuring synchronization between different processes running on the core, and also between different cores that are using the same coherent memory locations for the semaphore. A Load-Exclusive instruction tags a small block of memory for exclusive access. CTR.ERG defines the size of the tagged block as 16 words, one cache line.


A load/store exclusive instruction is any one of the following:

  • In the A64 instruction set, any instruction that has a mnemonic starting with LDX, LDAX, STX, or STLX.
  • In the A32 and T32 instruction sets, any instruction that has a mnemonic starting with LDREX, STREX, LDAEX, or STLEX.

If a Load-Exclusive instruction is performed to non-cacheable or device memory, and is to a region of memory in the SoC that does not support exclusive accesses, it causes a Data Abort exception with a Data Fault Status Code of either:

  • 0b110101, when using the long descriptor format.
  • 0b10101, when using the short descriptor format.

See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information about these instructions.

Treatment of intervening STR operations

Where there is an intervening store operation between an exclusive load and an exclusive store from the same core, the intermediate store does not produce any direct effect on the internal exclusive monitor.

After the exclusive load, the local monitor is in the Exclusive Access state. It remains in the Exclusive Access state after the store, and then returns to the Open Access state only after an exclusive store, a CLREX instruction, or an exception return.

However, if the exclusive code sequence accessed address is in cacheable memory, any eviction of the cache line containing that address clears the monitor. Arm recommends that no load or store instructions are placed between the exclusive load and the exclusive store, because these additional instructions can cause a cache eviction. Any data cache maintenance instruction can also clear the exclusive monitor.