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Arm Cortex-A55 Core Technical Reference Manual : Program flow prediction

Program flow prediction

The Cortex®-A55 core contains program flow prediction hardware, also known as branch prediction.

Branch prediction increases overall performance and reduces power consumption. With program flow prediction disabled, all taken branches incur a penalty that is associated with flushing the pipeline.

To avoid this penalty, the branch prediction hardware predicts if a conditional or unconditional branch is to be taken. For conditional branches, the hardware predicts if the branch is to be taken. It also predicts the address that the branch goes to, known as the branch target address. For unconditional branches, only the target is predicted.

The hardware contains the following functionality:

  • A BTAC holding the branch target address of previously taken branches.
  • Dynamic branch predictor history.
  • The return stack, a stack of nested subroutine return addresses.
  • A static branch predictor.
  • An indirect branch predictor.

Predicted and non-predicted instructions

Unless otherwise specified, the following list applies to A64, A32, and T32 instructions. As a rule the flow prediction hardware predicts all branch instructions regardless of the addressing mode, and includes:

  • Conditional branches.
  • Unconditional branches.
  • Indirect branches that are associated with procedure call and return instructions.
  • Branches that switch between A32 and T32 states.

The following branch instructions are not predicted:

  • Data-processing instructions using the PC as a destination register.
  • The BXJ instruction.
  • Exception return instructions.

T32 state conditional branches

A T32 unconditional branch instruction can be made conditional by inclusion in an If-Then (IT) block. It is then treated as a conditional branch.

Return stack

The return stack stores the address and instruction set state.

This address is equal to the link register value stored in R14 in AArch32 state or X30 in AArch64 state.

The following instructions cause a return stack push if predicted:

  • BL r14.
  • BLX (immediate) in AArch32 state.
  • BLX (register) in AArch32 state.
  • BLR in AArch64 state.
  • MOV pc,r14

In AArch32 state, the following instructions cause a return stack pop if predicted:

  • BX
  • LDR pc, [r13], #imm
  • LDM r13, {…pc}
  • LDM r13, {…pc}

In AArch64 state, the RET instruction causes a return stack pop.

As exception return instructions can change core privilege mode and security state, they are not predicted. These include:

  • LDM (exception return)
  • RFE
  • SUBS pc, lr
  • ERET