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Arm Cortex-A55 Core Technical Reference Manual : About the L2 memory system

About the L2 memory system

The Cortex®-A55 L2 memory system is required to interface the Cortex-A55 cores to the L3 memory system.

The L2 cache controller handles requests from the L1 instruction and data caches, and snoop requests from the L3 memory system. The L2 memory system forwards responses from the L3 system to the core, which can then take precise or imprecise aborts, depending on the type of transaction.

The L2 memory subsystem consists of:

  • An optional 4-way, set-associative L2 cache with a configurable size of 64KB, 128KB or 256KB. Cache lines have a fixed length of 64 bytes.
  • Optional ECC protection for tag, data, and L2 data buffer RAM structures.

The main features of the L2 memory system are:

  • Strictly exclusive with L1 data cache.
  • Pseudo-inclusive with L1 instruction cache.
  • Private per-core unified L2 cache.
  • 40-bit physical address space.
  • Physically indexed, physically tagged.