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Arm Cortex-A55 Core Technical Reference Manual : Optional integrated L2 cache

Optional integrated L2 cache

Data is allocated to the L2 cache only when evicted from the L1 memory system, not when first fetched from the system.

The exceptions to this rule are:

  • If the read-allocate hint is set, cacheable reads from the TLB or Instruction side (I-side) will be allocated in the L2 cache.
  • If the write-allocate hint is set, when the L1 enters write-streaming mode, cacheable writes will be allocated in the L2.
  • L2 prefetches issued by the L1 through a PLD or PRFM instruction are allocated in the L2 regardless of the read-allocate hint.

When non-temporal data is evicted from the L1 memory system, the data is sent directly to L3 and is not allocated in L2.

L2 RAMs are invalidated automatically at reset unless the debug recovery P-channel state is used.