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Arm Cortex-A55 Core Technical Reference Manual : Support for memory types

Support for memory types

The Cortex®-A55 core simplifies the coherency logic by downgrading some memory types.

  • Memory that is marked as both Inner Write-Back Cacheable and Outer Write-Back Cacheable is cached in the L1 data cache and the L2 cache.
  • All other memory types are Non-cacheable.

The additional attribute hints are used as follows:

Allocation hint
Determines the rules of allocation of newly fetched lines in the system, see Optional integrated L2 cache.
Transient hint

Allocating reads to the L1 data cache that have the transient bit set are allocated in the L1 cache and marked as most likely to be evicted according to the L1 eviction policy.

Writes that have the transient bit set are not allocated to the L1 cache but are allocated to the L2 cache instead.

Evictions from L1 cache marked as transient are not allocated in L2 cache.

The standard CHI attributes are passed to DSU with no modifications (except for translating architectural attributes to CHI attributes):

  • Allocate hint.
  • Cacheability (inner and outer are merged together, as the Cortex-A55 core only allocates both inner and outer cacheable memory).
  • Shareability.