You copied the Doc URL to your clipboard.

Arm Cortex-A55 Core Technical Reference Manual : AAarch32 and AArch64 behavior differences

AAarch32 and AArch64 behavior differences

The Cortex®-A55 core is an Arm®v8‑A compliant core that supports execution in both AArch32 and AArch64 states.

The following table shows the behavior differences between both execution states.

Table A5-2 AAarch32 and AArch64 behavior differences

  AArch32 AArch64
Address translation system The Armv8‑A address translation system resembles the Armv7 address translation system with Large Physical Address Extension (LPAE) and Virtualization Extensions. The Armv8‑A address translation system resembles an extension to the Long descriptor format address translation system to support the expanded virtual and physical address space.
Translation granule 4KB for both Virtual Memory System Architecture (VMSA) and LPAE. 4KB, 16KB, or 64KB for LPAE.
ASID size 8 bits. 8 or 16 bits, depending on the value of TCR_ELx.AS
VMID size 8 bits. 8 or 16 bits, depending on the value of VTCR_EL2.VS
PA size 40 bits only.

Maximum 40 bits.

Any configuration of TCR_ELx.IPS over 40 bits is considered as 40 bits. You can enable or disable each stage of the address translation independently.

The Cortex-A55 core also supports the Virtualization Host Extension (VHE) including ASID space for EL2. When VHE is implemented and enabled, EL2 has the same behavior as EL1.

See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information on concatenated translation tables and for address translation formats.