The three main functions of the MMU are to:
- Control the page table walk hardware that accesses translation tables in main memory.
- Translate Virtual Addresses (VAs) to Physical Addresses (PAs).
- Provide fine-grained memory system control through a set of virtual-to-physical address mappings and memory attributes that are held in translation tables.
Each stage of address translation uses a set of address translations and associated memory properties that are held in memory mapped tables called translation tables. Translation table entries can be cached into a Translation Lookaside Buffer (TLB).
The following table describes the components included in the MMU.
Table A5-1 TLBs and TLB caches in the MMU
|Instruction L1 TLB||15 entries, fully associative|
|Data L1 TLB||16 entries, fully associative|
|L2 TLB||1024 entries, 4-way set associative|
|Walk cache RAM||64 entries, 4-way set associative|
|IPA cache RAM||64 entries, 4-way set associative|
L2 TLB entries contain global and Address Space Identifiers (ASID) to prevent context switch TLB flushes.
The TLB entries contain a Virtual Machine Identifier (VMID) to prevent context switch TLB flushes on virtual machine switches by the hypervisor.
The Cortex®-A55 core supports a 40-bit physical address range, which allows 1TB of physical memory to be addressed.