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Arm Cortex-A55 Core Technical Reference Manual : Configuring MMU accesses

Configuring MMU accesses

Translation table walk can be performed in cacheable or non-cacheable regions. This is determined by the translation table walk memory attribute, which can be affected by several different configurations:

  • IRGN and ORGN bits in the TCR_ELx and VTCR_EL2 registers (or TTBR0/TTBR1_ELx register for short-descriptor translation table format), which define the memory type for translation table walk.
  • SCTRL_ELx.C and HCR_EL2.CD or HCR.CD, which affect the table walk to cacheable or non-cacheable memory.
  • Stage 2 memory attribute for stage 1 translation table walk, which affect the stage 1 translation table walk memory attribute.

For more information on the control fields, see the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

Only when the final translation table walk memory attribute is inner write-back and outer write-back and the cache is enabled, the translation table walk accesses the cacheable memory.