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Arm Cortex-A55 Core Technical Reference Manual : Hardware management of the Access flag and dirty state

Hardware management of the Access flag and dirty state

The Cortex®-A55 core includes the option to perform hardware updates to the translation tables in AArch64 state only.

These features are enabled in registers TCR_ELx and VTCR_EL2. To support the hardware management of dirty state, the DBM field is added to the translation table descriptors as part of Arm®v8.1‑A architecture.

The core supports hardware updates to the Access flag and to dirty state only when the translation tables are held in Inner Write-Back, Outer Write-Back Normal memory regions.

If software requests a hardware update in a region that is not Inner Write-Back or Outer Write-Back Normal memory, then the core returns an abort with the following encoding:

  • ESR.ELx.DFSC = 0b110001 for Data Aborts in AArch64.
  • ESR.ELx.IFSC = 0b110001 for Instruction Aborts in AArch64.

For the Cortex-A55 core, the following situations can cause hardware updates to the Access flag or to dirty state:

  • For a Store-Exclusive instruction to a memory location for which the DBM bit is 1 and the stage 1 AP[2] bit is 1, if the Store-Exclusive fails because the exclusive monitor is not in the exclusive state, the AP[2] bit in the translation table is updated.
  • For a Store-Exclusive instruction to a memory location for which the DBM bit is 1, and the stage 2 S2AP[1] bit is 0, if the Store-Exclusive fails because the exclusive monitor is not in the exclusive state, the S2AP[1] bit in the translation table is updated.
  • For a store to a memory location for which the DBM bit is 1, and the stage 1 AP[2] bit is 1, the AP[2] bit in the translation table is updated:
    • If the memory location generates a synchronous external abort on a write for a store to a memory location.
    • If the memory location generates a watchpoint on a write.
  • For a store to a memory location for which the DBM bit is 1, and the stage 2 S2AP[1] bit is 0, the S2AP[1] bit in the translation table is updated:
    • If the memory location generates a synchronous external abort on a write for a store to a memory location.
    • If the memory location generates a watchpoint on a write.
  • For a CAS or CASP instruction to a memory location for which the DBM bit is 1, and the stage 1 AP[2] bit is 1, if the compare fails, and the location is not updated, the AP[2] bit in the translation table is updated.
  • For a CAS or CASP instruction to a memory location for which the DBM bit is 1, and the stage 2 S2AP[1] bit is 0, if the compare fails, and the location is not updated, the S2AP[1] bit in the translation table is updated.

For more information about hardware updates of the Access flag and dirty state, see the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.