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Arm Cortex-A55 Core Technical Reference Manual : Memory Behavior

Memory Behavior

The Cortex®-A55 core supports all the Arm®v8‑A memory types.

However, the following behaviors are simplified and so for best performance their use is not recommended:

Write-Through Memory that is marked as Write-Through cannot be cached on the data-side and does not make coherency requests. On the instruction-side, areas that are marked as Write-Through and Write-Back can be cached in the L1 instruction cache. However, only areas marked as Write-Back can be cached in the L2 cache or the L3 cache.
Mixed inner and outer cacheabilityMemory that is not marked as inner and outer Write-Back cannot be cached on the data-side and does not make coherency requests. This applies to the memory type only, and not to the allocation hints. All caches within the cluster are treated as being part of the inner cacheability domain.

For more information on supported memory behaviors, see the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile