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Arm Cortex-A55 Core Technical Reference Manual : Support for Armv8‑A device memory types

Support for Arm®v8‑A device memory types

The Arm®v8‑A architecture includes memory types that replace the Armv7 Device and Strongly-ordered memory types. These device memory types have the following three attributes:

G – Gathering
The capability to gather and merge requests together into a single transaction.
R – Reordering
The capability to reorder transactions.
E – Early Write Acknowledgement
The capability to accept early acknowledge of transactions from the interconnect.

The legal combinations are described in the following table:

Table A5-3 Armv8‑A Device Memory Types

Memory Type



GRE Yes Similar to ‘Normal’ non-cacheable, but does not permit speculative accesses.
nGRE Yes Transactions may be re-ordered within the L3 memory system, or in the system interconnect.
nGnRE Yes Corresponds to ‘Device’ in Armv7.
nGnRnE Yes

Corresponds to ‘Strongly Ordered’ in Armv7.

Treated the same as nGnRE inside Cortex-A55, but reported differently on the bus interface.

For more information, see the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.