You copied the Doc URL to your clipboard.

Arm Cortex-A55 Core Technical Reference Manual : IPA cache RAM

IPA cache RAM

The IPA cache RAM holds mappings between intermediate physical addresses (IPAs) and physical addresses (PAs).

Only Non-secure EL1 and EL0 stage 2 translations use the IPA cache. When a stage 2 translation completes, the cache is updated. The IPA cache is checked whenever a stage 2 translation is required.

Like the L2 TLB, the IPA cache RAM can hold entries for different sizes.