A unified L2 TLB handles any misses from the L1 instruction and data TLBs.
- A 4-way, set-associative, 1024 entry cache.
- Supports all Virtual Memory System Architecture (VMSA) v8 block sizes, except for 1GB.
If a 1GB block is fetched, it is split into 512MB blocks and the appropriate block for the lookup is stored.
Accesses to the L2 TLB take a variable number of cycles, based on:
- Competing requests from the L1 TLBs.
- TLB maintenance operations in flight.
- Different page size mappings in use.