Core Wait for Event
WFE is a feature of the Arm®v8‑A architecture. It uses a locking mechanism based on events, to put the core in a low-power state by disabling most of the clocks in the core, while keeping the core powered up.
There is a small dynamic power overhead from the logic that is required to wake up the core from WFE low-power state. Other than this, the power that is drawn is reduced to static leakage current only.
A core enters into WFE low-power state by executing the
WFE instruction. When the
instruction executes, the core waits for all instructions in the core to complete before it
enters the idle or low-power state.
If the event register is set, execution of WFE does not cause entry into standby state, but clears the event register.
While the core is in WFE low-power state, the clocks in the core are temporarily enabled without causing the core to exit WFE low-power state when any of the following events are detected:
- An L3 snoop request that must be serviced by the core data caches.
- A cache or TLB maintenance operation that must be serviced by the core L1 instruction cache, data cache, TLB, or L2 cache.
- An APB access to the debug or trace registers residing in the core power domain.
- A GIC CPU access through the AXI4 stream channel.
Exit from WFE low-power state occurs on the assertion of the EVENTI input signal or one of the WFE wake-up events as described in the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.