Core Wait for Interrupt
WFI puts the core in a low-power state by disabling most of the clocks in the core, while keeping the core powered up.
There is a small dynamic power overhead from the logic that is required to wake up the core from WFI low-power state. Other than this, the power that is drawn is reduced to static leakage current only.
When the core executes the
instruction, the core waits for all instructions in the core to retire before it enters
low-power state. The
WFI instruction ensures that all
explicit memory accesses that occurred before the
instruction in program order have retired.
In addition, the
WFI instruction ensures
that store instructions have updated the cache or have been issued to the L3 memory
While the core is in WFI low-power state, the clocks in the core are temporarily enabled without causing the core to exit WFI low-power state when any of the following events are detected:
- An L3 snoop request that must be serviced by the core data caches.
- A cache or TLB maintenance operation that must be serviced by the core L1 instruction cache, data cache, TLB, or L2 cache.
- An APB access to the debug or trace registers residing in the core power domain.
- A GIC CPU access through the AXI4 stream channel.
Exit from WFI low-power state occurs when the core detects a reset or one of the WFI wake up events or when the AX14 stream channel accesses the GIC CPU interface. For more information, see the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.