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Arm Cortex-A55 Core Technical Reference Manual : Power domains

Power domains

The Cortex®-A55 core supports multiple power domains.

The following figure shows the power domains in the Cortex-A55 core. The colored boxes indicate the PDADVSIMD, PDCPU, and PDSYS power domains, with respective voltage domains shown in dotted lines.

Figure A4-2 Cortex-A55 Core Power Domains


The following figure shows the power domains in the Cortex-A55 cluster, where everything in the same color is part of the same power domain. The example shows four cores in the cluster. The number of cores can vary and the number of domains increase based on the number of cores present. This example only shows the power domains that are associated with the Cortex-A55 cores, and not the other power domains required for a cluster.

Figure A4-3 Cortex-A55 Power Domains


Note

You do not need to use the full flexibility that the Cortex-A55 clock, voltage, and power domains provide.

The Advanced SIMD and floating-point block in each core is also part of the power domain for that core. However, to support independent retention control, each Advanced SIMD and floating-point block also has its own power domain for isolation from the surrounding domain.

The following table shows the power domains that the Cortex-A55 core supports.

Table A4-1 Power domain description

Power domain Description
PDCPU<n>

This domain contains all ananke_cpu logic and cpu clock domain logic of the asynchronous bridge. It also includes the optional Advanced SIMD and floating-point block, the L1 and L2 TLBs, L1 and L2 core RAMs, and debug registers that are associated with the core.

<n> where n is the core number in the range 0-7. The number represents core 0, core 1, core 2, to core 7. If a core is not present, the corresponding power domain is not present.

PDADVSIMD<n>

This is an optional power domain for Advanced SIMD and floating-point block to implement dynamic retention.

<n> where n is the core number in the range 0-7. The number represents core 0, core 1, core 2, to core 7. If a core is not present, the corresponding power domain is not present.

PDSYS

This domain contains the cluster clock domain logic of the asynchronous bridge.

Clamping cells between power domains are inferred rather than instantiated in the RTL.