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Arm Cortex-A55 Core Technical Reference Manual : Power down sequence

Power down sequence

The Cortex®-A55 core uses the following power down sequence.

To power down a core, perform the following programming sequence:

  1. Save all architectural state.
  2. Configure the GIC distributor to disable or reroute interrupts away from this core.
  3. Set the CPUPWRCTLR.CORE_PWRDN_EN bit to 1 to indicate to the power controller that a powerdown is requested.
  4. Execute an Instruction Synchronization Barrier (ISB) instruction.
  5. Execute a WFI instruction.

After executing WFI and then receiving a powerdown request from the power controller, the hardware performs the following:

  • Disabling and flushing of caches (L1 and L2).
  • Removal of the core from coherency.

Note

When the CPUPWRCTLR.CORE_PWRDN_EN bit is set, executing a WFI instruction automatically masks all interrupts and wake-up events in the core. As a result, applying reset is the only way to wake up the core from this WFI.